With the current progress in scaling down MOS transistors to increasingly smaller dimensions, the trend is such that the dimensions involved will soon extend into the nanometer scale regime. As transistor geometries shrink, however, short-channel effects cause a variety of shifts in the behavior of MOS transistors away from conventional models.
In one aspect, the intrinsic gain of a short-channel MOS is around 20 dB, too low for many high-accuracy high-gain analog blocks. In another aspect, the gain variation due to temperature of a short-channel MOS can be up to 12 dB, complicating the design of short-channel temperature-insensitive analog blocks, such as bandgap and temperature sensor circuits.
One solution, commonly adopted in long-channel analog circuits, to improve the intrinsic gain of a transistor is to increase its channel length. Intuitively, widening the channel of a transistor increases its resistance, which, in turn, increases its intrinsic gain. In short-channel technology, however, this solution works adversely. In fact, an increase in the channel length of a short-channel MOS results in a decrease in the voltage required to deplete the channel, lowering the channel resistance and, consequently, the intrinsic gain of the MOS.
What is needed therefore is a high-gain MOS topology for short-channel analog circuits. Further, a MOS topology with reduced gain variation due to temperature is needed.